> For the complete documentation index, see [llms.txt](https://mujoseph.gitbook.io/mujoseph-docs/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://mujoseph.gitbook.io/mujoseph-docs/emma-mk1-drsstc/hardware-overview/electrical-design/pcb-design/current-sense.md). # Current Sense

## Role The *Current Sense PCB* takes the output current from the Over Current Detection (OCD) and Zero Crossing Detection (ZCD) current transformers (CT), converts them to voltage, applies conditioning, and then routes these voltage signals to the [*Motherboard PCB*](/mujoseph-docs/emma-mk1-drsstc/hardware-overview/electrical-design/pcb-design/motherboard.md) via an Ethernet cable. ## Design Intent As with the [*GDT Driver PCB*](/mujoseph-docs/emma-mk1-drsstc/hardware-overview/electrical-design/pcb-design/gdt-driver.md)*,* the *Current Sense PCB* is meant to be modular, allowing for quick evaluation of different signal conditioning topologies as well as providing a generic interface for external current transformers. The design intent of the *Current Sense PCB* was to evaluate the resilience of the current feedback signals (ZCD and OCD) to the noise from the EMI of the DRSSTC. The current feedback circuit and the driver are not physically co-located; a relatively long effective current loop exists (albeit shielded, via the Ethernet cable). Therefore, this configuration increases the susceptance of the circuit to the EMI, potentially leading to spurious ZCD and/or OCD events. ## Schematic Overview ### Current Transformer The initial selection for the current transformer was the [CST206-1A](https://www.triadmagnetics.com/item/current-sense-transformers/cst206-cst306-series-current-sense-transformers/cst206-1a-1) from Triad Magnetics. An inexpensive off-the-shelf CT was used to avoid having to construct one in-house. At the time of construction, the market for CTs at the peak current and resonant frequency of the *Emma Mk1* was limited. In fact, the *Emma Mk1* exceeds the operational frequency (200 kHz max) of the `CST206-1A` . After initial testing, the `CST206-1A` output became significantly distorted during extended operation, leading to poor inverter switching performance and OCD detection from excessive phase lag. The distortion was most likely caused by excessive core heating (from eddy currents) and the parasitic winding capacitance and leakage inductance exacerbating the CT output amplitude and phase distortion due to operating at a frequency exceeding its maximum rating. This could be mitigated partially by introducing significant phase lead via the [DRSSTC\_Driver](/mujoseph-docs/emma-mk1-drsstc/drsstc_driver-firmware-overview.md) firmware. However, this is not a sufficient solution due to the aforementioned temperature- and frequency-dependent parasitics. In the final implementation of the *Emma Mk1*, a pair of [1:1024 cascaded current transformers](/mujoseph-docs/emma-mk1-drsstc/hardware-overview/mechanical-design/feedback-current-transformers.md) were constructed by hand for both the ZCD and OCD feedback paths, which led to satisfactory inverter switching performance. ### Zero Crossing Detection (ZCD)

Current Sense PCB Rev B Zero Crossing Detection (ZCD) circuit

This circuit converts the current output, $$I\_{CT}$$, of the ZCD CT, `T1`, to a voltage, $$V\_{zcd}$$, with the following transfer function: $$ V\_{zcd}= I\_{CT}R\_{burden}+\frac{V\_{cc}}{2} = \frac{I\_{pri}}{N\_s}\cdot R\_{burden}+\frac{V\_{cc}}{2} $$ Where: * $$I\_{pri}$$ is the primary current \[$$\text{A}$$] * $$I\_{CT}$$ is the CT output current \[$$\text{A}$$] * $$R\_{burden}$$ is the CT burden resistor resistance (e.g., `R4` ) \[$$\Omega$$] * $$V\_{cc}$$ is the digital supply voltage (e.g., 3.3 V) \[$$V$$] * $$N\_s$$ is the CT secondary turn (e.g., 1024) Since the ZCD signal is fed to an internal comparator within the STM32 on the [*Motherboard*](/mujoseph-docs/emma-mk1-drsstc/hardware-overview/electrical-design/pcb-design/motherboard.md) PCB, the ZCD voltage signal is biased at mid-supply, and the non-inverting input of the comparator is connected to an internal DAC, which sets the compare threshold (e.g., $$V\_{cc}/2$$). `U1A` buffers the mid-supply bias so that it can be sampled by one of the internal ADCs within the STM32 so that the DAC output can be adjusted (and thus the comparator compare threshold) in real-time to accommodate any drift. In the *Emma Mk1*, this turned out to be unnecessary, so the circuit was left un-populated. ### :warning:ZCD Schematic Errata The ZCD schematic (left) is incorrect. Refer to the LTSpice schematic (right) for the actual ZCD schematic implemented in the *Emma Mk1*. * `D2` and `D3` in original schematic are not populated * Instead, a pair of leaded diodes are placed anti-parallel to each other across the CT burden resistor * `D4`, `D5`, `TVS2` and `U1` are not populated. Sampling DC bias via SMT32 ADC was not needed in the *Emma Mk1 DRSSTC* * `T1` is not populated; an external, hand-made CT is connected to `J3` via a twisted-pair, Molex connector (see [here](#current-transformer)) * `R4` is not populated. A leaded 22 $$\Omega$$ resistor is used instead to increase the gain due to the increased primary current attenuation from the hand-made CT (original [off-the-shelf CT](#current-transformer) attenuated the primary current by 100x; the hand-made CT has 1024x attenuation)

Corrected schematic
Diodes `D8` and `D9` clamp the ZCD voltage feedback signal to a diode drop above and below the mid-supply voltage ( V_{cc}/2 = 3.3/2 \approx 1.65\, V)

### Over Current Detection (OCD)

Th above circuit converts the current output, $$I\_{CT}$$, of the OCD CT, `T2`, to a rectified voltage, $$V\_{ocd}$$, with the following transfer function: $$ V\_{ocd}= \bigg|I\_{CT}R\_{burden}\bigg|= \bigg|\frac{I\_{pri}}{N\_s}\cdot R\_{burden}\bigg| $$ Where: * $$I\_{pri}$$ is the primary current \[ $$\text{A}$$ ] * $$I\_{CT}$$ is the CT output current \[ $$\text{A}$$ ] * $$R\_{burden}$$ is the CT burden resistor resistance ( e.g., `R9` + `R10` ) \[ $$\Omega$$ ] * $$N\_s$$ is the CT secondary turns (e.g., 1024 ) The max resolvable primary current by the OCD circuit is: $$ I\_{resolvable(max)}=\frac{V\_{cc}N\_s}{R\_{burden}} $$ Where: * $$R\_{burden}$$ is the CT burden resistor resistance \[$$\Omega$$] * $$N\_s$$ is the number of CT secondary turns (e.g., 1024) * $$V\_{cc}$$ is the STM32 supply voltage \[$$V$$] Any primary current greater than $$I\_{resolvable(max)}$$ will produce a voltage higher than the STM32 supply voltage and will need to be clamped to prevent damage to the MCU. ### :warning:OCD Schematic Errata * `T2` is not populated; an external, hand-made CT is connected to `J4` via a twisted-pair, Molex connector (see [here](#current-transformer)) * Burden resistors `R9` and `R10` are not populated. A leaded 3.3 $$\Omega$$ resistor is used instead to increase the gain due to the increased primary current attenuation from the hand-made CT (the original [off-the-shelf CT](#current-transformer) attenuated the primary current by 100x; the [hand-made CT](/mujoseph-docs/emma-mk1-drsstc/hardware-overview/mechanical-design/feedback-current-transformers.md) has 1024x attenuation) * The max resolvable primary current is $$3.3/3.3 \cdot1024 = 1024,A$$. * With an OCD limit of 800 A and a max PRF duty cycle of 8%, the burden resistor will dissapate $$\big\[(800/1024)^2\cdot 3.3\big]\cdot 0.08 \approx 161 ,\text{mW}$$. Therefore, a 1 W resistor is more than sufficient. ### Primary Current Sensing

Current Sense PCB Rev B low-side, bi-directional current sensing circuit ( [1] )

This low-side, bi-directional current sense circuit was added to the *Current Sense PCB* to enable the eventual sampling of the un-distorted primary current via one of the internal ADCs of the STM32. The intention is to provide insight into the primary current behavior during topload arc/streamer generation and arc strike events. {% hint style="warning" %} In the current implementation of the *Emma Mk1* firmware, this is not implemented. {% endhint %} The transfer function for the above schematic: $$ V\_{cs}= I\_{CT}\cdot R\_{burden}\cdot G\_{cs}+ V\_{bias}=\underbrace{\frac{I\_{pri}}{N\_s}\cdot R\_{burden}\cdot G\_{cs}}*{V*{diff}} + \underbrace{V\_{bias}}*{V*{cm}} $$ $$ G\_{cs}=\frac{R\_{17}}{R\_{16}}\quad\quad\quad(\text{current sense amplifier gain}) $$ $$ V\_{bias} = \frac{R\_{12}}{R\_{11}+R\_{12}} = \frac{V\_{cc}}{2} $$ Where: * $$I\_{pri}$$ is the primary current \[ $$\text{A}$$ ] * $$R\_{burden}$$ is the CT burden resistor ( e.g., `R15` ) \[ $$\Omega$$ ] * $$I\_{CT}$$ is the CT output current \[ $$\text{A}$$ ] * $$V\_{cc}$$ is the digital supply voltage ( e.g., 3.3 V ) \[ $$V$$ ] * $$N\_s$$ is the CT secondary turns ( e.g., 1024 ) #### Current Sense Circuit Output Voltage Considerations: Differential ADC If the output of the current sense amplifier, $$V\_{cs}$$, is sampled using a single ADC channel configured in differential mode with the non-inverting input set to $$V\_{INP}=V\_{cs}$$ and the inverting input $$V\_{INN}=V\_{bias}$$; care must be taken to not violate the ADC's input common mode mode rating, $$V\_{CMIN}$$ :

STM32G474RE internal ADC characteristics ( source: datasheet )

Referring to the above table, with the positive reference voltage set to $$V\_{REF+} = V\_{cc}$$ and the negative reference voltage tied to ground ($$V\_{REF-}=0, V$$), the input common mode range is: $$ V\_{bias}-180,\text{mV}\le V\_{CMIN} \le V\_{bias}+180,\text{mV} $$ Essentially, the average of the inverting and non-inverting ADC input voltages must be within $$\pm,180,\text{mV}$$ of the mid-supply voltage (in this case 1.65 V). Since the differential signal is only applied to the non-inverting input, care must be taken when choosing the CT burden resistor (`R15`) and the amplifier feedback network resistors (`R16` and `R17`), lest the effective gain of the system may cause the voltage average across the two ADC input pins to deviate too far from the mid-supply voltage and violate the above inequality. The differential input pins, $$V\_{INP}$$ and $$V\_{INN}$$, of the STM32 ADC channel would see the following: $$ V\_{INP} = V\_{cs}=V\_{diff}+V\_{cm}\quad\quad V\_{INN}=V\_{cm} $$ The input common mode voltage seen by the ADC: $$ V\_{CM}=\frac{V\_{INP}+V\_{INN}}{2} $$ Substituting: $$ V\_{CM}=\frac{V\_{diff}+V\_{cm}+V\_{cm}}{2}=\frac{V\_{diff}}{2}+V\_{cm} $$ From the current sense transfer function equation: $$V\_{diff}= \frac{I\_{pri}}{N\_s}\cdot R\_{burden}\cdot G\_{cs}$$ and $$V\_{cm}=V\_{bias}$$. Substituting into the input common mode range equation above: $$ V\_{bias}-180,\text{mV}\le \bigg(\frac{1}{2}\bigg)\cdot \frac{I\_{pri}}{N\_s}\cdot R\_{burden}\cdot G\_{cs} + V\_{bias} \le V\_{bias}+180,\text{mV} $$ The $$V\_{bias}$$ terms cancel, and the entire inequality is multiplied by 2: $$ -360,\text{mV}\le \frac{I\_{pri}}{N\_s}\cdot R\_{burden}\cdot G\_{cs} \le +360,\text{mV} $$ Re-writing: $$ \bigg|\frac{I\_{pri}}{N\_s}\cdot R\_{burden}\cdot G\_{cs} \bigg| \le 360,\text{mV} $$ Therefore, for a worst-case, peak primary current, the CT burden resistor and current sense feedback resistors would have to be chosen so that the resultant voltage is below 360 mV. This clearly illustrates the disadvantage of only applying the differential voltage signal to one of the ADC differential input pins. This is a poor use of the ADC's nominal differential range. The better method would be to sample the current sense output voltage and the bias voltage via two separate, synchronized, single-ended ADC channels, then remove the DC bias from the measurement after digitization. Better methods exist but would require a schematic revision. ### Motherboard PCB Interface

Current Sense PCB Rev B Ethernet interface for connecting
to the Motherboard PCB

The *Current Sense PCB* connects to the *Motherboard PCB* through the Ethernet female receptacle, `J1`. See the respective [*Motherboard PCB* documentation](/mujoseph-docs/emma-mk1-drsstc/hardware-overview/electrical-design/pcb-design/motherboard.md#current-sense-interface) for more information. The 100 mil (2.54 mm) pitch pin header, `J2`, provides a duplicate interface for debugging. ## PCB Design Ground pours were placed on both the top and bottom layers of the PCB, and then via stitched to the internal reference plane (internal layer 1, center image) to provide a low-impedance return path for any coupled noise from the DRSSTC EMI.

Current Sense PCB Rev B
Internal Layer 1: GND

To help mitigate the conducted EMI from the connected Ethernet cable, a split ground, `GND_EXT`, and power plane, `3V3_EXT`, was implemented around the RJ45 jack, `J1` .

`GND_EXT` pour surrounding `J1` on
Internal Layer 1 ( Ground )

`3V3_EXT` pour surrounding `J1` on
Internal Layer 2 ( Power )

The separate power and ground planes are then connected to the rest of the PCB via a common-mode choke, `L1`, and a ferrite bead, `FB1`, to attenuate the conducted common-mode and differential noise, respectively (see below).

Conducted EMI filter
Common-mode
choke `L1` and ferrite bead `FB1`

`L1` spans the split ground/power planes on the top layer

The high-frequency component of a signal follows the path of least inductance, which is the path on the ground/return plane directly below the PCB microstrip. The area directly below the microstrip is where the field coupling is strongest. Thus the forward and return current magnetic fields cancel via the [right-hand-rule](https://en.wikipedia.org/wiki/Right-hand_rule), yielding the low characteristic inductance condition, making the described current path the smallest possible loop (resulting in less *generated* EMI and less susceptance *to* EMI) [\[2\]](#references). To preserve the smallest possible loop for the aforementioned reasons, the analog signals are routed across the split ground plane directly underneath the common-mode choke, `L1`, on the bottom layer (see below).

Analog signals from `J1` being routed on the bottom layer
across the internal layer 1 split ground plane ( not shown ), directly underneath
`L1` on the top layer ( not shown )

### PCB Manufacturing Specifications * Fabrication: [JLCPCB](https://jlcpcb.com/) * Layers: 4 * Internal Layer 1: GND * Internal Layer 2: Power * Copper weight: 1 oz outer, 0.5 oz inner * Plating: ENIG * Board thickness: 62 mil (1.6 mm) * Assembly: [JLCPCB](https://jlcpcb.com/) ## Gallery

*Emma Mk1 Current Sense* Rev A PCB bringup

## References 1. [TI-Analog Engineer's Circuit Cookbook: Amplifiers](https://www.ti.com/lit/pdf/SLYY137) 2. [TI-Grounding in mixed-signal systems demystified (part 2)](https://www.ti.com/lit/pdf/slyt512)